As semiconductor geometries continue to become smaller and smaller, new techniques arise in achieving ever decreasing footprints for device functionality. Memory devices, especially, because there are many millions of identical cells in a single memory chip, are the focus of intensive miniaturization efforts.
Many modern memory devices use FET technology. Flash, or non-volatile, memory uses stored charges to provide the equivalent of a gate voltage a cross a source/drain channel. A memory cell voltage/current relationship is such that, when a voltage is applied between the source and drain, VDS, a current flow, IDS is measurable. When a gate voltage is very low, IDS is low. When a gate voltage is very high, IDS is high, near device saturation. At so me medial gate voltage, a high los indicates an erased, “one,” state and a low IDS indicates a written, “zero” state. This medial gate voltage is the normal threshold voltage, or VT, in the erased state. A charge stored between the gate node and the channel can modulate threshold voltage, VT.
As feature sizes shrink, the size of a stored charge approaches that of a single electron. One technique for shrinking the footprint of memory cells is by allowing cells to share gates and source/drain regions in a mirrored-bit arrangement. This sharing is enabled by storing more than one charge in a single shared charge-trapping layer. Each charge affects the current flow in one direction or polarity more than the other so the source and drain can swap roles depending on which bit of the mirrored-bit cell is being read.
However, as mirrored bit cells shrink, they approach their theoretical size limits. Further, making them smaller requires that the separated regions of the common charge trapping layer be moved closer together, thereby reducing the probability of distinguishing between them. A need exists then for a means of reducing the requisite memory cell footprint while maintaining a distinction between stored charges. Furthermore, any such device should be able to be fabricated using existing semiconductor fabrication processes.